Contact

Electronics & Communication Engineering · Adikavi Nannaya University

Semiconductor
nanofabrication &
process engineering

My focus is nanofabrication and process integration - the fabrication flow from oxidation and implantation through lithography, etch and deposition. Since I do not yet have a fab to run experiments in, I work the other way round: build open-source simulators of those process steps, and use SPC, yield analytics and machine learning to read what process data is telling you.

View projects Fabrication training
04Fab & nanofab programmes
07Projects & prototypes
04Preprints & datasets
03Internships
01

Profile

I am an electronics undergraduate on a diploma-to-degree pathway, working toward semiconductor nanofabrication and process integration. My fabrication grounding comes from four programmes - SPARC NanoX at IIT Hyderabad, the Semiconductor Nanofabrication Summer School at CeNSE, IISc Bengaluru, Semiconductor Fabrication 101 from Purdue / UT Austin / Intel, and Duke's Nanotechnology: A Maker's Course - plus hands-on electrical characterization of optoelectronic assemblies across three internships.

Because a fab is not yet available to me, my method is to model the process instead: implement the classical models for oxidation, implantation, diffusion and pattern transfer, benchmark them against known results, and treat the simulator as a way to reason about the physics a real line runs on. Alongside that I work on the data side of manufacturing - statistical process control, yield analytics and ML - where the same instinct applies: find the signal, then say how confident you are in it. Every project carries a limitations list: the modules that are incomplete, the figures that come from public datasets rather than a fab, and the validation still to be done.

Core interests

  • Nanofabrication and process integration
  • Cleanroom operations
  • Semiconductor process modeling and simulation
  • Computational lithography and device/process modeling
  • Process characterization and metrology
  • 2D materials and optoelectronics
  • Applied machine learning; embedded systems
02

Selected projects

Status = self-assessed maturity
In development

AttoFab

Open-source semiconductor process simulator

An education-first fabrication simulator built on classical, citable textbook physics: thermal oxidation (Deal-Grove, with (111)/(100) orientation dependence), Gaussian ion implantation, Fick's-law diffusion, LOCOS-style masked oxidation, mask expose/develop, and cellular-automaton anisotropic and isotropic etch/deposition. The 1D and 2D engines are complete; a hand-rolled GDSII parser and 3D wafer mesh work, with integration still partial. Ships with a physics-regression bench, a FastAPI backend, two web frontends and a CLI.

Scope & limitations Lithography is limited to mask expose/develop; 3D lithography is not implemented. Oxidation substitutes material in place rather than modelling volume expansion, so oxide growth alone creates no topography - only etch does. The Pearson-IV implant model is gated off until its moment-matching is correct, and some 3D flows still run only through a Rust example.

github.com/LKSH-GNDJ/AttoFab
RustPython / FastAPIGDSIIMIT license
Concept

Silicon Grove / Double-PINN

Process-to-device modeling

A research scaffold for connecting simplified process-physics and device-physics models through a differentiable workflow - exploring how target device behaviour might inform process choices.

Scope & limitations Not yet validated against TCAD or experimental fabrication data.

Physics-informed MLDifferentiable modelingResearch prototyping
Prototype

Wafer Process Monitoring & Yield Analytics

Time-series drift and anomaly detection

Time-series analytics for detecting process drift and anomalies, built on statistical process-control methods - EWMA and CUSUM - combined with model-based anomaly detection and root-cause analysis.

Scope & limitations Results come from evaluated datasets and prototypes, not from a production semiconductor fab.

SPCTime-seriesAnomaly detectionRoot-cause analysis
Benchmark

SECOM ML Benchmark

Semiconductor manufacturing dataset

Analysis of the public SECOM dataset - 1,567 observations and 104 failure labels - using multiple ensemble models and feature-analysis methods to separate yield-limiting signals from sensor noise.

Reading the number Reported ROC-AUC of 0.95 is a dataset result. It is not production-line performance and should not be read as one.

Ensemble MLXGBoostSHAPModel evaluation
Prototype

AttoCore

Neuromorphic RTL prototype

A synthesizable leaky integrate-and-fire neuron architecture with synaptic crossbar and STDP concepts. A configuration audit identified and corrected a fixed-width accumulator overflow issue.

Scope & limitations RTL testbenches still require execution in a Verilog simulator.

RTLDigital designVerilog conceptsNeuromorphic computing
Prototype

CAPHA

Embedded / IoT & TinyML

Embedded and IoT project work covering edge anomaly-detection concepts and TinyML workflows, with inference intended to run locally rather than in the cloud.

Scope & limitations Concept and workflow stage; deployed field data is not yet part of the work.

Embedded systemsIoTTinyMLEdge analytics
Prototype

AttoSense

Multimodal NLU service

An intent-analysis service built on zero-shot intent discovery and multimodal auditing: a FastAPI microservice wrapping Groq Whisper for speech transcription and Llama-3.2-Vision for reading visual input, so an intent can be resolved from voice and image as well as from text.

Scope Personal project. The description covers architecture and capability; no benchmark or deployment figures are attached to it.

FastAPIGroq WhisperLlama-3.2-VisionZero-shot NLU
03

Experience

Embedded & IoT Intern

Uni Convergence Technologies

May 2025 - Jun 2025

High-precision electrical characterization and functional quality control for optoelectronic PCB assemblies. Optimized production and testing workflows across multiple assembly phases, and wrote structured testing protocols to evaluate hardware quality and reduce initial assembly defects. Worked on TinyML and edge anomaly-detection concepts within embedded/IoT workflows.

Product Intern

Sri Nikhil Krishna Solutions

Nov 2023 - May 2024

Supported electrical characterization and functional quality checks of optoelectronic PCB assemblies, including high-precision measurement procedures, production workflow optimization and the development of structured test protocols to minimize initial assembly defects.

AI & ML Intern

Infosys Springboard

Feb 2026 - Apr 2026

Project Associate in the NLU Bot Trainer program, training and optimizing data pipelines for industrial intent classification. Analysed natural-language dataset patterns to refine intent detection accuracy and model processing logic, working across the intent-classification bot's training workflows and data pipelines.

04

Fabrication training

Programme training · no process ownership claimed
202601

SPARC NanoX - Phase 1

IIT Hyderabad

Semiconductor and nanofabrication programme, Phase 1.

202602

Semiconductor Nanofabrication Summer School

CeNSE, IISc Bengaluru

Nanofabrication summer school at the Centre for Nano Science and Engineering.

202503

Semiconductor Fabrication 101

Purdue / UT Austin / Intel

Foundations of the semiconductor fabrication flow, delivered jointly by Purdue University, UT Austin and Intel.

202404

Nanotechnology: A Maker's Course

Duke / NC State / UNC · Coursera

Maker-oriented course on nanotechnology fabrication and the tools used to build at that scale.

05

Research & education

Preprints · datasets
SSRN preprint · 2026

Analytical Redundancy for False Alarm Suppression in Edge-based Semiconductor Process Control

DOI 10.2139/ssrn.7211483

Academic background

  • B.Tech, Electronics & Communication Engineering

    University College of Engineering, Adikavi Nannaya University (AKNU)

    Expected Apr 2027

  • Diploma, Electronics & Communication Engineering

    Government Polytechnic, Anaparthi · SBTET

    May 2024

06

Technical skills

Fab & process

  • Process flow: oxidation → litho → etch/deposition
  • Classical process-model implementation
  • Computational lithography fundamentals
  • SPC · DOE concepts
  • Yield analytics
  • Root-cause analysis

Programming / data

  • Python
  • Rust
  • C / C++
  • Data preprocessing
  • Time-series analysis
  • Ensemble ML · XGBoost · SHAP
  • Model evaluation
  • FastAPI · Git · Docker

Hardware / systems

  • Electrical characterization
  • Verilog / RTL concepts
  • OpenLane
  • SkyWater 130 nm PDK exposure
  • Embedded systems · TinyML
  • Altium PCB

Research practice

  • Technical documentation
  • Literature-based model comparison
  • Reproducible experiments
  • Limitations tracking
07

Certifications

PCB Basic DesignAltium · 2025
Six Sigma White Belt2025
Principles of Generative AIInfosys · 2025
McKinsey Forward Program2025
ACE Multicloud Network AssociateAviatrix · Dec 2025

08 - Contact

Get in touch

Open to conversations on nanofabrication and process integration, semiconductor process modeling, computational lithography, and yield/SPC analytics. The quickest route is LinkedIn.

linkedin.com/in/lokesh-gundoju
LinkedIn ↗ Scholar ↗ GitHub ↗ ORCID ↗